Field of the Invention
This invention relates to a semiconductor device, and more particularly to a high integration technique for a semiconductor device. The present invention further relates to a process of producing a semiconductor device of the type mentioned.
Description of the Related Art
In recent years, to apply the technique of microelectronics to industrial machinery and home appliances, a VLSI (Very-Large-Scale integration) circuit which is a further integrated LSI (Large Scale Integration) is developed and commercially available. In the case of a semiconductor memory device, for example, the storage capacity has been increased a thousand-fold in these ten years. The development of such high integration is realized by miniaturization of the size of a unit element, which constitutes a semiconductor device, by using a method called proportional scaling.
FIG. 1 is a perspective sectional view of a semiconductor device showing a basic structure of a MOS (Metal-Oxide-Semiconductor) field effect transistor (hereinafter referred to briefly as "MOSFET") for use with a conventional semiconductor integrated circuit. The description below about the MOSFET is mainly based on "Physics of Semiconductor Devices (2nd Edition)" by S. M. Sze.
Referring to FIG. 1, the MOSFET shown is a four-terminal element (in the figure, one of the terminals is not shown) and includes a P-type semiconductor substrate 52, two N.sup.+ diffused regions 54 and 56 formed in a spaced relationship from each other on a main surface of the P-type semiconductor substrate 52, a gate oxide film 60 formed on a region of the main surface of the P-type semiconductor substrate 52 between the two N.sup.+ diffused regions 54 and 56, a gate electrode 62 formed of a metal on the gate oxide film 60, a source electrode 64 made of a metal and provided on the N.sup.+ diffused region 54, and a drain electrode 66 made of a metal and provided on the N diffused region 56. A thick field oxide film 58 is provided around the MOSFET and isolates the same from other elements.
The source electrode 64 is connected to a fixed ground potential. A gate voltage V.sub.G is applied to the gate electrode 62. A drain voltage V.sub.D is applied to the drain electrode 66. The P-type semiconductor substrate 52 is connected to a substrate potential equal to or lower than the ground potential.
Basic device parameters which define operation of the MOSFET described above are such as follows.
(1) Channel length L: this is a distance between two N.sup.+ -P junctions, one between the N.sup.+ diffused region 54 and the substrate 52 and the other one between the other N.sup.+ -P diffused region 56 and the substrate 52 just below the gate electrode 62.
(2) Channel width Z.
(3) Thickness d of the gate oxide film 60.
(4) Junction thickness r.sub.j : this is a thickness of diffusion of the N.sup.+ diffused regions 54 and 56.
(5) Substrate concentration N.sub.A : this is a concentration of an impurity in the P-type semiconductor substrate 52.
Referring to FIG. 1, operation of the MOSFET will be described below. When no voltage is applied to the gate electrode 62, the N.sup.+ diffused region 54 and P-type semiconductor substrate 52, and the N.sup.+ diffused region 56 and P-type semiconductor substrate 52 correspond to the two P-N junctions connected in a back-to-back relationship. In this instance, an electric current flowing between the N.sup.+ diffused regions 54 and 56 is a leak current caused by a reverse-bias voltage.
If a sufficiently high positive voltage is applied to the gate electrode 62, an inversion layer (or "channel") is formed in a region just below the gate electrode 62 between the two N.sup.+ diffused regions 54 and 56. The N.sup.+ diffused regions 54 and 56 are thus coupled to each other by way of a conducting surface so that a large current is allowed to flow through the channel. The conductivity of the channel thus formed is modulated by the gate voltage V.sub.G to be applied to the gate electrode 62. The back-surface contact (or "substrate contact") of the two P-N junctions is connected to the substrate potential which is selected so that a reverse-bias may be applied to the P-N junctions. In addition to the five device parameters listed hereinabove, also the substrate potential is a parameter which provides a variation to the channel conductivity.
A change in behavior of the MOSFET by a change of the individual device parameters will be described in the following. If, for example, the channel width Z is reduced, the amount of area where field oxide films 58 are formed on the opposite sides of the gate increases relatively. Consequently, the threshold voltage V.sub.th of the MOSFET becomes higher. If the thickness d of the gate oxide film 60 increases, also the threshold voltage V.sub.th becomes higher. If the junction depth r.sub.j increases, an electric current is formed not just below the gate in the inversion layer but at a relatively deep location of the substrate 52. Consequently, punch-throughs become likely to occur. If the junction depth r.sub.j is small, an electric field will concentrate at edge portions of the N.sup.+ diffused regions 54 and 56 on the channel side, causing hot electron effect, resulting in a change of characteristics, and the withstand voltage of the MOSFET becomes low. If the substrate concentration N.sub.A is low, depletion layers around the N.sup.+ diffused regions 54 and 56 are likely to expand, whereby punch-throughs are apt to be caused. It is also known that, if the substrate concentration N.sub.A is higher, then the threshold voltage V.sub.th becomes higher.
As high integration of semiconductor integrated circuit devices proceeds, the channel length L naturally decreases. As the channel length L decreases, instead of the one-dimensional potential distribution as in a conventional semiconductor integrated circuit device, a two-dimensional potential distribution appears and a high electric field is formed in the channel region.
If it is assumed that the doping concentration in a channel region is predetermined, when the channel length L decreases, the order of the width of depletion layers formed at the P-N junctions between the semiconductor substrate 52 and the N.sup.+ diffused regions 54 and 56 becomes similar to that of the channel length L. The potential distribution in a channel region relies upon a longitudinal electric field .epsilon..sub.y and a transverse electric field e.sub.X. The former depends upon the gate potential V.sub.G and the substrate potential. The latter depends upon the drain potential V.sub.D. In other words, the gradual-channel approximation of .epsilon..sub.y &gt;&gt;.epsilon..sub.X no more stands, and the potential distribution in the channel region becomes two-dimensional.
Such two-dimensional potential distribution has an unfavorable influence on the movement of carriers passing through the channel and gives rise to deterioration in characteristics at a voltage of the MOSFET lower than its threshold level. The two-dimensional potential distribution has a bad influence also on relationships of the threshold voltage V.sub.th with the channel length L and the bias voltage, giving rise to an undesirable change in characteristics of the MOSFET. Further, also a problem takes place that the electric current is saturated by a punch through.
Increase in electric field intensity in the channel region caused by decrease in channel length L gives rise to reliance on the mobility of carriers moving in the channel region upon the electric field and sometimes results in velocity saturation of carriers. If the electric field intensity further increases, the velocity of carriers moving in the channel becomes very high in the neighborhood of the N.sup.+ diffused region 56. The carriers are thus suddenly increased in number in the neighborhood of the N.sup.+ diffused region 56 by a large amount of energy of the carriers. Consequently, the substrate current by leakage may be increased, or a parasitic bipolar transistor formed in the semiconductor substrate 52 may be caused to operate.
A high electric field formed due to decrease of the channel length L gives rise to the formation of a plurality of hot carriers, and such hot carriers charge up oxide films such as the gate oxide film 60. Charged-up oxide films often give rise to variation in threshold voltage V.sub.th of the MOSFET and hence to deterioration in conductivity of the MOSFET.
As described hereinbefore, the higher the degree of integration of the semiconductor integrated circuit device is, the shorter the channel length L of the MOSFET becomes. The decrease in channel length L complicates the operation of the MOSFET, making the characteristics of the element very unstable. Accordingly, the structure of a semiconductor integrated circuit device at present is difficult to cope with higher integration.